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Chapter 1: What’s New in ISE Design Suite
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Beginning with ISE Design Suite 13.2, Xilinx requires users to select all IOSTANDARDs
and pin placement in their design prior to generating a bitstream. Please see Xilinx
Answer Record 41615 for more information
Note: For additional Known Issues, please see Xilinx Answer Record 40905 .
7 Series Devices in Limited Access – Virtex-7 XT and Artix-7
In this release, the following devices are Limited Access and are license controlled:
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Xilinx Virtex-7 XT
Xilinx Artix-7
Limited Access devices are currently Beta-level quality and access requires a device-
specific license. Contact your Sales Representative for more information about obtaining
the required license.
Table 1-1 provides information on which Artix-7 software features are not fully supported
(noted limitations or license required).
Table 1-1:
Artix-7 Software Features Not Fully Supported
Feature
Synthesis - 3 rd party
IP Support
All Devices Available
Implementation Tools
7 Series Transceiver Wizard
Design Preservation and Team
Design
Supported in Limited Access
Yes
(Refer to the section Synthesis-
3rd Party )
Yes
(Refer to the section IP Support )
Limited (A8/A15 support in
Release 13.3)
Yes
No
No
Device-Specific
License Required
No
No
Yes
Yes
N/A
N/A
14
Partial Reconfiguration
ChipScope
SSO and SSN
Bitstream Generation
No
No
No
No
www.xilinx.com
N/A
N/A
N/A
N/A
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
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